1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
/**
* CLKCTRL Generated Driver File
*
* @file clkctrl.c
*
* @ingroup clkctrl
*
* @brief This file contains the driver code for CLKCTRL module.
*
* version CLKCTRL Driver Version 1.1.4
*
* @version Package Version 2.0.10
*/
/*
© [2025] Microchip Technology Inc. and its subsidiaries.
Subject to your compliance with these terms, you may use Microchip
software and any derivatives exclusively with Microchip products.
You are responsible for complying with 3rd party license terms
applicable to your use of 3rd party software (including open source
software) that may accompany Microchip software. SOFTWARE IS ?AS IS.?
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS
SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY
KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE
FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP?S
TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL NOT
EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR
THIS SOFTWARE.
*/
#include "../clock.h"
void CLOCK_Initialize(void)
{
ccp_write_io((void*)&(CLKCTRL.MCLKCTRLA),(1 << CLKCTRL_CLKOUT_bp) // CLKOUT enabled
| CLKCTRL_CLKSEL_EXTCLK_gc // CLKSEL External clock
);
ccp_write_io((void*)&(CLKCTRL.MCLKCTRLB),CLKCTRL_PDIV_DIV2_gc // PDIV Divide by 2
| (0 << CLKCTRL_PEN_bp) // PEN disabled
);
ccp_write_io((void*)&(CLKCTRL.OSC32KCTRLA),(0 << CLKCTRL_RUNSTDBY_bp) // RUNSTDBY disabled
);
ccp_write_io((void*)&(CLKCTRL.OSCHFCTRLA),CLKCTRL_AUTOTUNE_OFF_gc // AUTOTUNE OFF
| CLKCTRL_FRQSEL_4M_gc // FRQSEL 4 MHz system clock (default)
| (0 << CLKCTRL_RUNSTDBY_bp) // RUNSTDBY disabled
| CLKCTRL_ALGSEL_BIN_gc // ALGSEL BIN
);
ccp_write_io((void*)&(CLKCTRL.OSCHFTUNE),0x0 // TUNE 0x0
);
ccp_write_io((void*)&(CLKCTRL.XOSC32KCTRLA),CLKCTRL_CSUT_1K_gc // CSUT 1k cycles
| (0 << CLKCTRL_ENABLE_bp) // ENABLE disabled
| (0 << CLKCTRL_LPMODE_bp) // LPMODE disabled
| (0 << CLKCTRL_RUNSTDBY_bp) // RUNSTDBY disabled
| CLKCTRL_SEL_XTAL_gc // SEL XTAL
);
ccp_write_io((void*)&(CLKCTRL.MCLKCTRLC),(0 << CLKCTRL_CFDEN_bp) // CFDEN disabled
| CLKCTRL_CFDSRC_XOSCHF_gc // CFDSRC XOSCHF
| (0 << CLKCTRL_CFDTST_bp) // CFDTST disabled
);
ccp_write_io((void*)&(CLKCTRL.MCLKINTCTRL),(0 << CLKCTRL_CFD_bp) // CFD disabled
| CLKCTRL_INTTYPE_INT_gc // INTTYPE INT
);
ccp_write_io((void*)&(CLKCTRL.MCLKINTFLAGS),(0 << CLKCTRL_CFD_bp) // CFD disabled
);
ccp_write_io((void*)&(CLKCTRL.XOSCHFCTRLA),CLKCTRL_CSUTHF_256_gc // CSUTHF 256
| (1 << CLKCTRL_ENABLE_bp) // ENABLE enabled
| CLKCTRL_FRQRANGE_24M_gc // FRQRANGE 24M
| (1 << CLKCTRL_RUNSTBY_bp) // RUNSTBY enabled
| CLKCTRL_SELHF_XTAL_gc // SELHF XTAL
);
ccp_write_io((void*)&(CLKCTRL.MCLKTIMEBASE),0x18 // TIMEBASE 24
);
// System clock stability check by polling the status register.
while(!(CLKCTRL.MCLKSTATUS & CLKCTRL_EXTS_bm))
{
}
}
void CFD_Enable(CLKCTRL_CFDSRC_t cfd_source)
{
/* Enable Clock Failure Detection on main clock */
ccp_write_io((uint8_t *) & CLKCTRL.MCLKCTRLC, cfd_source | CLKCTRL_CFDEN_bm);
}
void CFD_Disable(void)
{
/* Disable Clock Failure Detection on main clock */
ccp_write_io((uint8_t *) & CLKCTRL.MCLKCTRLC, CLKCTRL.MCLKCTRLC & ~CLKCTRL_CFDEN_bm);
}
/**
End of File
*/
|
