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authorJoshua Drake <Joshua.Ellis.Drake@gmail.com>2023-10-11 17:09:59 -0500
committerJoshua Drake <Joshua.Ellis.Drake@gmail.com>2023-10-11 17:09:59 -0500
commitd8201407a1979cea24747aeed0a9177dec73d17d (patch)
tree7d2a8dc750f166c558a6727e279622206e49aef0 /_autosave-Resistor Bank Control Board.kicad_pcb
parentdca5740ec11bc311404d0110b72a606e913a0dbe (diff)
Made a lot of progress on the PCB from OBX :)
Diffstat (limited to '_autosave-Resistor Bank Control Board.kicad_pcb')
-rw-r--r--_autosave-Resistor Bank Control Board.kicad_pcb4491
1 files changed, 0 insertions, 4491 deletions
diff --git a/_autosave-Resistor Bank Control Board.kicad_pcb b/_autosave-Resistor Bank Control Board.kicad_pcb
deleted file mode 100644
index 2874cb2..0000000
--- a/_autosave-Resistor Bank Control Board.kicad_pcb
+++ /dev/null
@@ -1,4491 +0,0 @@
-(kicad_pcb (version 20221018) (generator pcbnew)
-
- (general
- (thickness 1.6)
- )
-
- (paper "A4")
- (layers
- (0 "F.Cu" signal)
- (1 "In1.Cu" signal)
- (2 "In2.Cu" signal)
- (31 "B.Cu" signal)
- (32 "B.Adhes" user "B.Adhesive")
- (33 "F.Adhes" user "F.Adhesive")
- (34 "B.Paste" user)
- (35 "F.Paste" user)
- (36 "B.SilkS" user "B.Silkscreen")
- (37 "F.SilkS" user "F.Silkscreen")
- (38 "B.Mask" user)
- (39 "F.Mask" user)
- (40 "Dwgs.User" user "User.Drawings")
- (41 "Cmts.User" user "User.Comments")
- (42 "Eco1.User" user "User.Eco1")
- (43 "Eco2.User" user "User.Eco2")
- (44 "Edge.Cuts" user)
- (45 "Margin" user)
- (46 "B.CrtYd" user "B.Courtyard")
- (47 "F.CrtYd" user "F.Courtyard")
- (48 "B.Fab" user)
- (49 "F.Fab" user)
- (50 "User.1" user)
- (51 "User.2" user)
- (52 "User.3" user)
- (53 "User.4" user)
- (54 "User.5" user)
- (55 "User.6" user)
- (56 "User.7" user)
- (57 "User.8" user)
- (58 "User.9" user)
- )
-
- (setup
- (stackup
- (layer "F.SilkS" (type "Top Silk Screen"))
- (layer "F.Paste" (type "Top Solder Paste"))
- (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
- (layer "F.Cu" (type "copper") (thickness 0.035))
- (layer "dielectric 1" (type "prepreg") (thickness 0.1) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
- (layer "In1.Cu" (type "copper") (thickness 0.035))
- (layer "dielectric 2" (type "prepreg") (thickness 1.24) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
- (layer "In2.Cu" (type "copper") (thickness 0.035))
- (layer "dielectric 3" (type "prepreg") (thickness 0.1) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
- (layer "B.Cu" (type "copper") (thickness 0.035))
- (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
- (layer "B.Paste" (type "Bottom Solder Paste"))
- (layer "B.SilkS" (type "Bottom Silk Screen"))
- (copper_finish "None")
- (dielectric_constraints no)
- )
- (pad_to_mask_clearance 0)
- (pcbplotparams
- (layerselection 0x00010fc_ffffffff)
- (plot_on_all_layers_selection 0x0000000_00000000)
- (disableapertmacros false)
- (usegerberextensions false)
- (usegerberattributes true)
- (usegerberadvancedattributes true)
- (creategerberjobfile true)
- (dashed_line_dash_ratio 12.000000)
- (dashed_line_gap_ratio 3.000000)
- (svgprecision 4)
- (plotframeref false)
- (viasonmask false)
- (mode 1)
- (useauxorigin false)
- (hpglpennumber 1)
- (hpglpenspeed 20)
- (hpglpendiameter 15.000000)
- (dxfpolygonmode true)
- (dxfimperialunits true)
- (dxfusepcbnewfont true)
- (psnegative false)
- (psa4output false)
- (plotreference true)
- (plotvalue true)
- (plotinvisibletext false)
- (sketchpadsonfab false)
- (subtractmaskfromsilk false)
- (outputformat 1)
- (mirror false)
- (drillshape 1)
- (scaleselection 1)
- (outputdirectory "")
- )
- )
-
- (net 0 "")
- (net 1 "+24V")
- (net 2 "GND")
- (net 3 "Net-(IC23-SW)")
- (net 4 "Net-(IC23-BOOT)")
- (net 5 "+5V")
- (net 6 "Net-(IC25-VCAP_OR_VDDCORE)")
- (net 7 "Net-(IC25-VDD)")
- (net 8 "Net-(JP1-B)")
- (net 9 "Net-(IC25-OSCI{slash}CLKI{slash}AN13{slash}CN30{slash}RA2)")
- (net 10 "Net-(IC25-OSCO{slash}CLKO{slash}AN14{slash}CN29{slash}RA3)")
- (net 11 "Net-(D1-A)")
- (net 12 "Net-(D2-K)")
- (net 13 "Net-(D2-A)")
- (net 14 "Net-(D3-K)")
- (net 15 "Net-(D3-A)")
- (net 16 "Net-(D4-K)")
- (net 17 "Net-(D4-A)")
- (net 18 "/Gate 1")
- (net 19 "/Gate 5")
- (net 20 "/Gate 7")
- (net 21 "SPI_MOSI")
- (net 22 "SPI_CHAIN")
- (net 23 "/Gate 9")
- (net 24 "/Gate 6")
- (net 25 "/Gate 4")
- (net 26 "/Gate 3")
- (net 27 "/Gate 10")
- (net 28 "unconnected-(IC21-OUT11-Pad17)")
- (net 29 "unconnected-(IC21-OUT12-Pad18)")
- (net 30 "SPI_SS")
- (net 31 "SPI_SCLK")
- (net 32 "/Gate 8")
- (net 33 "/Gate 2")
- (net 34 "/Gate 11")
- (net 35 "/Gate 15")
- (net 36 "/Gate 17")
- (net 37 "SPI_MISO")
- (net 38 "/Gate 19")
- (net 39 "/Gate 16")
- (net 40 "/Gate 14")
- (net 41 "/Gate 13")
- (net 42 "/Gate 20")
- (net 43 "unconnected-(IC22-OUT11-Pad17)")
- (net 44 "unconnected-(IC22-OUT12-Pad18)")
- (net 45 "/Gate 18")
- (net 46 "/Gate 12")
- (net 47 "Net-(IC23-EN)")
- (net 48 "Net-(IC23-RT{slash}SYNC)")
- (net 49 "Net-(IC23-FB)")
- (net 50 "Net-(IC23-PG)")
- (net 51 "Net-(IC25-MCLR{slash}VPP{slash}RA5)")
- (net 52 "unconnected-(IC25-CVREF+{slash}VREF+{slash}DAC1REF+{slash}AN0{slash}C3INC{slash}CN2{slash}RA0-Pad2)")
- (net 53 "unconnected-(IC25-CVREF-{slash}VREF-{slash}AN1{slash}RA1-Pad3)")
- (net 54 "PGD")
- (net 55 "PGC")
- (net 56 "I2C_SDA")
- (net 57 "I2C_SCLK")
- (net 58 "unconnected-(IC25-SOSCI{slash}AN15{slash}~{U2RTS}{slash}U2BCLK{slash}CN1{slash}RB4-Pad11)")
- (net 59 "unconnected-(IC25-SOSCO{slash}SCLKI{slash}AN16{slash}PWRLCLK{slash}~{U2CTS}{slash}CN0{slash}RA4-Pad12)")
- (net 60 "unconnected-(IC25-PGED3{slash}AN17{slash}ASDA1{slash}SCK2{slash}IC4{slash}OC1E{slash}CLCINA{slash}CN27{slash}RB5-Pad14)")
- (net 61 "unconnected-(IC25-AN21{slash}SDA1{slash}T1CK{slash}U1RTS{slash}U1BCLK{slash}IC2{slash}OC4{slash}CLC1O{slash}CTED4{slash}CN21{slash}RB9-Pad18)")
- (net 62 "unconnected-(IC25-SDI2{slash}IC1{slash}OC5{slash}CLC2O{slash}CTED3{slash}CN9{slash}RA7-Pad19)")
- (net 63 "unconnected-(IC25-DAC1OUT{slash}AN12{slash}HLVDIN{slash}~{SS2}{slash}IC3{slash}OC2B{slash}CTED2{slash}INT2{slash}CN14{slash}RB12-Pad23)")
- (net 64 "unconnected-(IC25-DAC2OUT{slash}CVREF{slash}OA1IND{slash}OA2IND{slash}AN10{slash}C3INB{slash}RTCC{slash}C1OUT{slash}OCFA{slash}CTED5{slash}INT1{slash}CN12{slash}RB14-Pad25)")
- (net 65 "/Coil 1")
- (net 66 "/Coil 2")
- (net 67 "/Coil 3")
- (net 68 "/Coil 4")
- (net 69 "/Coil 5")
- (net 70 "/Coil 6")
- (net 71 "/Coil 7")
- (net 72 "/Coil 8")
- (net 73 "/Coil 9")
- (net 74 "/Coil 10")
- (net 75 "/Coil 11")
- (net 76 "/Coil 12")
- (net 77 "/Coil 13")
- (net 78 "/Coil 14")
- (net 79 "/Coil 15")
- (net 80 "/Coil 16")
- (net 81 "/Coil 17")
- (net 82 "/Coil 18")
- (net 83 "/Coil 19")
- (net 84 "/Coil 20")
- (net 85 "MCLR")
- (net 86 "unconnected-(J3-Pad6)")
- (net 87 "Net-(J4-Pin_2)")
-
- (footprint "Library:HDRV2W67P0X254_1X2_508X241X858P" (layer "F.Cu")
- (tstamp 05a4cc51-643d-4610-9a85-62aa4c2fe975)
- (at 98.46 104.5)
- (descr "69190-202HLF")
- (tags "Connector")
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- (path "/5d4a7f07-12db-4031-a559-a5f4428cdbcc/2874aef7-fccc-48a3-82a4-65cf17723235")
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- (tstamp 80b3528e-884e-4369-a735-08c8a7be8476)
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- (fp_text value "Jumper_2_Open" (at 0 0) (layer "F.SilkS") hide
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- (pad "1" thru_hole rect (at 0 0) (size 1.725 1.725) (drill 1.15) (layers "*.Cu" "*.Mask")
- (net 85 "MCLR") (pinfunction "A") (pintype "passive") (tstamp 41c5c314-cae3-4523-a43b-fc5992962387))
- (pad "2" thru_hole circle (at 2.54 0) (size 1.725 1.725) (drill 1.15) (layers "*.Cu" "*.Mask")
- (net 8 "Net-(JP1-B)") (pinfunction "B") (pintype "passive") (tstamp 97faf335-a271-4ea0-8910-b3c773afc8de))
- (model "69190-102HLF.stp"
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- (footprint "Library:PXP01530QLJ" (layer "F.Cu")
- (tstamp 09295089-474c-4d84-865c-774036b79867)
- (at 113.94 92.09)
- (descr "SOT8002-1_2022")
- (tags "MOSFET (P-Channel)")
- (property "Height" "0.9")
- (property "Manufacturer_Name" "Nexperia")
- (property "Manufacturer_Part_Number" "PXP015-30QLJ")
- (property "Mouser Part Number" "771-PXP015-30QLJ")
- (property "Mouser Price/Stock" "https://www.mouser.co.uk/ProductDetail/Nexperia/PXP015-30QLJ?qs=MyNHzdoqoQIbg8Lyue8mKw%3D%3D")
- (property "Sheetfile" "Resistor Bank Control Board.kicad_sch")
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