ICD class com.microchip.mcc.mcu16.systemManager.icd.Icd INTERNAL OSCILLATOR class com.microchip.mcc.mcu16.systemManager.clk.Clock Interrupt Module class com.microchip.mcc.mcu16.interruptManager.InterruptManager MSSP1 class com.microchip.mcc.mcu16.modules.mssp.MSSP MSSP2 class com.microchip.mcc.mcu16.modules.mssp.MSSP Main Manager class com.microchip.mcc.mcu16.mainManager.MainManager Pin Module class com.microchip.mcc.mcu16.pinManager.PinManager RESET class com.microchip.mcc.mcu16.systemManager.reset.RESET System Module class com.microchip.mcc.mcu16.systemManager.DefaultSystemManagerMcu16 TMR1 class com.microchip.mcc.mcu16.modules.tmr.TMR WATCHDOG class com.microchip.mcc.mcu16.systemManager.wdt.Wdt enabled disabled disabled 20000000 10000000 8000000 31000 20000000 Primary Oscillator disabled disabled UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED AVAILABLE AVAILABLE AVAILABLE UNSUPPORTED NOTAVAILABLE AVAILABLE AVAILABLE UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED NOTAVAILABLE UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED UNSUPPORTED AVAILABLE UNSUPPORTED NOTAVAILABLE NOTAVAILABLE UNSUPPORTED UNSUPPORTED AVAILABLE AVAILABLE UNSUPPORTED UNSUPPORTED disabled 1:2 enabled enabled disabled disabled 8000000.0 disabled 0 FOSC disabled disabled 20000000 enabled disabled disabled Center frequency disabled Port I/O enabled (CLKO disabled) enabled 0 7 4 1 5 2 6 3 0 1 0 4 1 7 5 2 6 3 0 1 1 0 1 0 0 7 1 6 5 2 3 4 1 0 0 7 1 6 5 2 3 4 1 0 0 1 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0 31 32 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 12544 512 0 0 0 0 0 0 0 0 1:8 disabled FRC/2 disabled no clock failure unlocked FRCDIV out of lock PRI Switch is Complete disabled disabled Center frequency enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled enabled 0 disabled FOSC disabled 5000000.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ISR_MSSP1_BCLI ISR_MSSP1_SSPI SPI Master 1 enabled disabled disabled enabled enabled End enabled 1 0 1 0 0 1 15 7 14 6 8 10 0 2 1 11 5 4 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 42 0 0 0 128 OFF disabled disabled 1 1 0 Idle:Low, Active:High enabled FOSC/(2 * (BRG_Value_SPI + 1)) no_overflow no_collision acknowledge disabled received disabled disabled disabled disabled disabled ackseq disabled disabled disabled disabled disabled disabled 100ns OFF disabled disabled 1 0 RCinprocess_TXcomplete Idle to Active lastbyte_address stopbit_notdetected write_noTX startbit_notdetected End dontupdate Clock Stretch 100000 ISR_MSSP2_BCLI ISR_MSSP2_SSPI I2C Slave 1 disabled enabled enabled disabled disabled Middle disabled 1 0 1 0 0 1 15 7 14 6 8 10 0 2 1 11 5 4 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 1 7 0 46 1 24 0 128 OFF disabled disabled 1 7 0 Clock Stretch enabled 7 Bit no_overflow no_collision acknowledge disabled received disabled disabled disabled disabled enabled ackseq disabled enabled disabled disabled disabled disabled 300ns OFF enabled disabled 1 0 RCinprocess_TXcomplete Idle to Active lastbyte_address stopbit_notdetected write_noTX startbit_notdetected Standard Speed dontupdate IO_RA0 IO_RA1 IO_RA4 IO_RB6 IO_RB7 IO_RB8 IO_RB9 ISR_Pin Module_CNI output output disabled disabled output disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled output output output output %DESELECT% %DESELECT% disabled disabled disabled enabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled none none none none none none none none none none none none none none none none none none none none none none none none disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled PDIP28 disabled disabled disabled enabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled enabled enabled 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 20528 0 0 0 0 0 0 0 0 0 448 0 164 21567 digital digital digital digital digital digital digital analog digital analog digital digital digital analog analog digital digital digital digital disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled 1 disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear clear disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled enabled enabled enabled disabled clear output output input output output input input input input input output input output input output input input input input output output output output 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled disabled 4 2 14 12 10 1 0 2 0 1 0 3 2 1 128 64 0 4 0 24 8 16 0 2 3 1 32 0 0 7 1 6 5 2 3 4 0 128 64 0 32 0 0 1 2 3 0 96 64 32 16 0 0 128 0 8 4 0 32 0 160 128 16 0 0 10 7 4 14 1 11 8 5 15 2 12 9 6 3 13 64 0 15 3 3 186 66 255 95 OFF OFF OFF OFF PGx1 CSDCMD ON HS HS SOSCHP PRI OFF HP DIG BOR3 V18 PRI ON ON OFF OFF PR128 PS32768 OFF disabled ISR_TMR1_TI 10000000 1.5000064 1.5000064 FOSC/2 0 58593 customTmrMode 10000000 1.6777216 0.0000512 256 39062.50000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1.5 1 16 Bit FALSE 65535 0 3 2 1 1 0 2 0 1 0 1 0 1 0 1 0 1 58593 32816 0 58593 1:256 FOSC/2 SOSC disabled enabled disabled disabled OFF enabled disabled 1 0 31000 135.300s CLOCK_LPRC enabled disabled mcc_generated_files/interrupt_manager.h 1ea0d12f1bfc7d92451919bd91e62714d8b7607658fa3d052e992a52ead88491 mcc_generated_files/pin_manager.h 080951689f95c4fc6350b1c256f03e85811ad476358298f6bd9507a53e443397 mcc_generated_files/tmr1.c abb80bb4d96b79d150f5ffe5f6a7ce5d22e1677f7d8e6eaa365b04e5193a9fdd mcc_generated_files/mssp1_spi.c 7d1e76be4f44e0c3033e4839463fd15c463956f0ac4eda99aaa104aaa5c079f9 mcc_generated_files/system.c b8c2da52b3923af46bd8d6dcc1feef6a3e3bf6b52a29859e42180ab2a32d42ef main.c 62990fd6c74361665b0487f7568abd48176fe4f567cce543690db2a436d03a07 mcc_generated_files/tmr1.h 91624125bcff3c356fc988e1e58df48db056543108919b7d8719137be50c965f mcc_generated_files/mssp1_spi.h 6028633bb6a6513606b543b57eac40d4690f44ec6865eafa03aba9a6dedfaca6 mcc_generated_files/clock.h 3d193f5928f2ec9cfcc6ad65b919ebcd72aa3fdf95637843efb6ac6949857aae mcc_generated_files/traps.h 1b2e427e275d3221008b6176bdff465ef4ae43cdbacc3650ebfa64360d5e7780 mcc_generated_files/clock.c 0cab06910a07845a0da3552256a704d1ec16f9ef27d26c5c2a1ba5dec11acd11 mcc_generated_files/traps.c c7984bb4b7a599f4c99e44fc894a33a2dd98187ecab007be4d47056b24237362 mcc_generated_files/mssp2_i2c.c 6e7ff380be6bfa8569ce806b04616f042f51a41c2e06f4c339035a06136ba6ed mcc_generated_files/mssp2_i2c.h f5c84331b873ea4ceec9269263d2a30d0cecd046dd89d75a2893edba9af2bf4c mcc_generated_files/mcc.h 1a2656005993f58131bc11eab9e2531d9b5906420afb3a6004e6fc273c27387c mcc_generated_files/system.h 44d3c3480770ee3961b77104442e62a091fb55f9d960f457c1e2f846d865b145 mcc_generated_files/interrupt_manager.c 2573e4437a3f520326772d81954754941c54d2d22996ef96e2bfeae062bbc345 mcc_generated_files/mcc.c 1b7975b399876b7768383891408cc730991c9803158bdd114f9238963196ebf8 mcc_generated_files/pin_manager.c d6ae875a31f2cde86a7ac4a78c80bb9d8bea3b27027a0aff60cafd4f1c59b7e3